1. Field of the Invention
The present invention relates to a shared main memory type multiprocessor system arranged to have a switch connection, and more particularly to a multiprocessor system which is suitable to sequential control of memory accesses among processors, the sequential control having coherence control of a cache located inside of each processor.
2. Description of the Related Art
In order to improve performance of a computer, a multiprocessor system is widely used which is arranged to use plural processors at a time. The multiprocessor system is divided into a distributed memory type and a shared main memory type. The former is arranged to prepare a main memory for each processor, while the latter is arranged to share a main memory among relevant processors. The latter is more likely to be programmed than the former because the latter serves to manage the data shared among the processors more easily than the former. Hence, the latter is more widely used.
The multiprocessor system is arranged to allow the relevant processors to be operated independently by exchanging data among the processors if necessary while the system is in operation. In exchanging data, the shared main memory type multiprocessor is operated so that one processor may read a value written on a main memory by another processor. This kind of data exchange among the processors needs sequential control of memory accesses among the processors. Concretely, in a case that one processor reads out the data written by another processor, the system needs to guarantee that this read is executed not before but after writing the data.
Herein, the representative arrangement of the shared main memory type multiprocessor will be described with reference to FIGS. 12 and 13. FIG. 12 shows a bus type multiprocessor, in which CPUs 5100 to 5130 are connected through a memory bus 5150 and operate to make access to a main memory 5140 through this memory bus 5150. The accesses may be serialized by the memory bus 5150. This serialization is more likely to control the sequence of writing and reading for exchanging the data. However, disadvantageously, the amount of accessing from the CPUs 5100 to 5130 to the main memory 5140 is limited by the neck of the memory bus 5150.
On the other hand, the switch connection type multiprocessor shown in FIG. 13 is arranged so that the CPUs 5200 to 5230 are individually connected to the main memory 5240. The switch connection type is characterized by low interference in each CPULs access on the main memory. For example, the access of the CPU 5200 onto the main memory 5240 through a line 5250 has no influence on the accessing paths 5260 to 5280 between the other CPUs 5210 and the main memory 5240. In an actual arrangement, a multistage switch is often provided between each of the CPUs 5200 to 5230 and the main memory 5240, in which case substantial interference may take place. However, unlike the bus type, the switch connection type has no element of completely serializing the CPU1s accesses on the main memory. Hence, the interference is negligible. As a result, the switch connection type realizes high accessing performance. On the other hand, this type of multiprocessor is arranged so that the CPUs are operated individually. This makes it difficult to guarantee the memory access sequence among the processors.
JP-A-10-187634 has disclosed a switch connection type shared main memory type multiprocessor system having a function of rapidly controlling memory access sequence among the processors. Concretely, an instruction for synchronization is prepared in the processor, and the memory access is serialized by using the transaction to be output in response to this instruction. This serialization is used for controlling the sequence of writing and reading among the processors.
A cache is widely used as a technique of speeding up the processor. The multiprocessor system having such a cache for each processor must maintain cache coherence (cache coherence control). The cache coherence control is executed for updating the previous data on the cache or purging it if one processor updates the data having the same memory address as the data registered in the cache of another processor. In order to guarantee the reading of correct data in exchanging the data, it is necessary to execute the cache coherence control for the target data.
It is therefore an object of the present invention to provide a multiprocessor system having an instruction for synchronizing the processors which system is arranged to guarantee cache coherence.
It is a further object of the present invention to provide a multiprocessor system which is arranged to execute memory access sequential control and cache coherence control not independently but together at once, which will make the data swap between the processors more efficient.
The multiprocessor system prepares a synchronize instruction in each relevant processor and serializes the accesses on the main memory and guarantees completion of the coherence control by using a transaction to be output from each processor in response to the instruction. Concretely, the multiprocessor realizes the following four functions.
(1) Each processor operates to output all the transactions of the instructions executed before the synchronize instruction to the main memory and then output the transaction by the synchronize instruction. This transaction is output to both of the main memory and the cache coherence controller.
(2) The main memory provides a mechanism of stopping the access to the main memory done by the source processor when it receives the transaction for synchronization. When the main memory receives the transactions for synchronization from all the processors, the main memory restarts the access to be given from the processors. This function makes it possible to serialize the accesses to the main memory from the processors.
(3) When the cache coherence controller receives the transactions for synchronization from all the processors, the cache coherence controller operates to complete the coherence control about the transactions previous to the transaction for synchronization and notify each processor of the completion of the coherence control.
(4) Between when the transaction for synchronization is received by each processor and when the notice of completion from the cache coherence controller is received by each processor, each processor interrupts the execution of the following instructions. It does not restart these instructions until the notice of completion is received. This function makes it possible to guarantee the completion of the cache coherence control.